System and method for initiating a serial data transfer between two clock domains

ABSTRACT

A system and method for transferring a data stream between devices having different clock domains. The method initiates a serial data stream between a transmitter and a receiver. The transmitter operates according to a first clock having a first clock rate, and the receiver operates according to a second clock having a second clock rate. A ratio between the second clock rate and the first clock rate is an integer number greater than or equal to one. A first state is provided over a serial line between the transmitter and the receiver One or more start bits are provided over the serial line. The start bits indicate a second state different from the first state. One or more ratio bits are provided over the serial line after the start bit. The ratio bits indicate the ratio between the second clock rate and the first clock rate. The start bits are received. Using a transition between the first state and the second state evident in receiving each of the start bits, the ratio bits are received. The remainder of the serial data stream is received at appropriate intervals of the second clock rate.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to data communications, and moreparticularly to a system and method for initiating a serial datatransfer between a first device clocked according to a first clock and asecond device clocked according to a second clock.

[0003] 2. Description of the Related Art

[0004] In computer systems, especially computer systems includingdevices that may operate according to differing internal clocks withdifferent clock rates, some mechanism is needed to assure that datatransfers can occur between the devices. Typically, synchronoustransfers are used to guarantee that data transferred from one device toanother is received properly. In a synchronous transfer, the clockingsignal is generated by the sending device and transmitted along with thedata, so that the data can be properly clocked as sent. When the sendingand receiving devices operate according to different clock rates, datatransfers are usually limited to the clock rate of the slower device.

[0005] One solution to speeding up transfer rates is to use anasynchronous transfer method so that high transfer rates may be achievedbetween devices operating at different clock rates. In an asynchronoustransfer, the clock is not transmitted with the data. One problem thatarises is that the asynchronous transfers must be initiated between thedevices. What is needed is a system and method for transmitting a datastream between devices operating in differing clock domains, which mayhave differing clock rates.

SUMMARY OF THE INVENTION

[0006] The problems outlined above are in large part solved by a systemand method for transferring a data stream between devices havingdifferent clock domains. In an exemplary computer system, one or moreprocessors are each coupled to a bridge through separate high speedconnections, which in one embodiment each include a pair ofunidirectional address buses with respective source-synchronous clocklines and a bi-directional data bus with attendant source-synchronousclock lines. System memory and

[0007] Broadly speaking, a method is contemplated for initiating aserial data stream between a transmitter and a receiver. The transmitteroperates according to at least a first clock having a first clock rate,and the receiver operates according to at least a second clock having asecond clock rate. A ratio between the second clock rate and the firstclock rate is an integer number greater than or equal to one. The methodcomprises providing a first state over a serial line between thetransmitter and the receiver. The method also includes providing one ormore start bits over the serial line. The start bits indicate a secondstate different from the first state. The method also provides one ormore ratio bits over the serial line after the start bit. The ratio bitsindicate the ratio between the second clock rate and the first clockrate. The method receives the one or more start bits. Using a transitionbetween the first state and the second state evident in receiving eachof the start bits, the method receives the one or more ratio bits. Themethod also includes receiving a remainder of the serial data stream atappropriate intervals of the second clock rate.

[0008] A computer system is also contemplated. Broadly speaking, thecomputer system comprises a memory, logic, and at least one processor.The memory is configured to store initialization information for thecomputer system. The initialization information begins with a start bitand a ratio bit. The ratio bit is encoded with the ratio between asecond clock rate and a first clock rate. The logic is coupled to thememory for transmitting the initialization information. The logic isconfigured to operate according to the first clock rate and to transmitthe initialization information at the first clock rate. The processor iscoupled to receive a first system clock operating at the first clockrate and a second system clock operating at the second clock rate. Theprocessor is configured to operate according to the second system clock.The processor is further coupled to the logic with a serial line overwhich to receive the initialization information. The logic is configuredto transmit the initialization information over the serial line to theprocessor. The logic is further configured to transmit a first stateover the serial line prior to the start bit. The start bit includes asecond state different from the first state. The processor is furtherconfigured to receive the start bit and to use a transition between thefirst state and the second state evident in receiving the start bit toreceive the ratio bit. The processor is further configured to decode theratio bit to determine the first clock rate in order to receive theremainder of the initialization information from the logic.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Other objects and advantages of the invention will becomeapparent upon reading the following detailed description and uponreference to the accompanying drawings in which:

[0010]FIG. 1 is a block diagram of an embodiment of a computer systemincluding two processors with separate buses coupling the processors toa bridge;

[0011]FIG. 2A is a block diagram of an embodiment of one of theprocessors and the bridge of FIG. 1 configured to accept two systemclock signals from a system clock;

[0012]FIG. 2B is a block diagram of an alternative embodiment of thesystem clock of FIG. 2A, where the system clock provides a single clocksignal over more than one clock line;

[0013]FIG. 3 is a block diagram of an embodiment of one of theprocessors and the bridge of FIG. 1, including input signals to theprocessor and the bridge as well as exemplary signals exchanged betweenthe processor and the bridge, wherein the bridge includes a ROM forstoring configuration data;

[0014]FIG. 4 is a block diagram of an embodiment of one of theprocessors and the bridge of FIG. 1, including exemplary address, data,and control signals exchanged between the processor and the bridge;

[0015]FIG. 5 is a block diagram of an embodiment of a system fortransferring a serial data stream from one device to another device,when the sending device and the receiving device operate according todifferent internal clocks;

[0016]FIG. 6A is an exemplary timing diagram of an embodiment ofoperations of the system of FIG. 5 when the sending device is clocked atbase clock rate that is equal to the receiving device;

[0017]FIG. 6B is an exemplary timing diagram of an embodiment ofoperations of the system of FIG. 5 when the sending device is clocked atbase clock rate that is one-half the base clock rate of the receivingdevice;

[0018]FIG. 7 is a flowchart of an embodiment of a method for initiatingoperation of the computer system of FIG. 1;

[0019]FIG. 8 is a flowchart of an embodiment of a method for inputtingthe processor clock rate ratio to the processor, such as is shown inFIG. 7;

[0020]FIG. 9 is a flowchart of an embodiment of a method forinitializing the processor using a SIP stream; and

[0021]FIG. 10 is a flowchart of an embodiment of a method forinitializing source-synchronous clocking between one of the processorsand the bridge of FIG. 1.

[0022] While the invention is susceptible to various modifications andalternative forms, specific embodiments thereof are shown by way ofexample in the drawings and will herein be described in detail. Itshould be understood, however, that the drawings and detaileddescription thereto are not intended to limit the invention to theparticular form disclosed, but on the contrary, the intention is tocover all modifications, equivalents and alternatives falling within thespirit and scope of the present invention as defined by the appendedclaims.

DETAILED DESCRIPTION OF THE INVENTION

[0023] Turning to FIG. 1, a block diagram of an embodiment of ageneralized computer system 100 is illustrated. A first processor 110Aand a second processor 110B each couple to a bridge 130 through separateprocessor buses. Both the first processor 110A and the second processor110B are preferably configured to perform memory and I/O operationsusing their respective processor buses. In one embodiment, processors110A and 110B implement the x86 instruction set architecture. Otherembodiments may implement any suitable instruction set architecture. Thebridge 130 is further coupled to a memory 140. The memory 140 ispreferably configured to store data and instructions accessible to boththe first processor 110A and the second processor 110B, as well as othersystem devices. The memory 140 may be comprised of SDRAM (SynchronousDynamic Random Access Memory), RDRAM (Rambus DRAM) [RDRAM and RAMBUS areregistered trademarks of Rambus, Inc.], or any other suitable memorytype. An advanced graphics port device (AGP) 150 is also optionallycoupled to the bridge 130. As shown, a Peripheral Component Interconnect(PCI) bus 160 is also coupled to the bridge 130. A variety of I/Ocomponents may be coupled to the PCI bus 160.

[0024] It is noted that in embodiments of the computer system 100including a legacy bus, such as an Industry Standard Architecture (ISA)bus, the bridge 130 is often referred to an a northbridge 130, with thebridge (not shown) between the PCI bus 160 and the legacy bus referredto as a southbridge. It is also noted that in the illustratedembodiment, the bridge 130 is the system master for the computer system100. While the illustrated embodiment includes two processors 110A and110B, it is noted any number of processors 110 may be included in thecomputer system 100 as desired.

[0025] In the illustrated embodiment, as the system master, the bridge130 operates to coordinate communications between processors 110A and110B, the memory 140, and the AGP device 150, as well as devices coupledto the PCI bus, etc. The bridge 130 maintains coherency for datatransfers among the devices of the computer system 100 by probingprocessor 110A and/or processor 110B for memory locations accessed bythe other processor 110A or 110B, the AGP device 150, or a PCI device onthe PCI bus 160, etc.

[0026] Turning now to FIG. 2A, a block diagram of an embodiment of oneof the processors 110A and the bridge 130 of FIG. 1 are illustrated. Asshown, a system clock 210 is coupled to provide a first system clockCLKIN 215 and a second system clock RSTCLK 220 to each of the processor110A and the bridge 130. The bridge 130 is shown operating according toat least one of the two system clocks, CLKIN 215 and/or RSTCLK 220. Theprocessor 110A receives the RSTCLK 220 and the CLKIN 215. Processor 110Ainputs first system clock CLKIN 215 into a PLL 225 and generates aprocessor clock PCLK 230. Processor clock PCLK 230 preferably operatesat a frequency that is a multiple of the first system clock CLKIN 215.The processor clock signal PCLK 230 is divided by a constant value tocreate PCLKOUT 235, which is routed out of the processor 110A and backinto the processor 110A as PCLKIN 240. The constant value used to dividethe processor clock signal PCLK 230 to create PCLKOUT 235 is preferablythe same as the multiple used to create the processor clock signal PCLK230 from the first system clock CLKIN 215. PCLKIN 240 is used as thefeedback clock signal for the PLL 225.

[0027] Thus, the system clock 210 may provide two clock signals to eachof the processor 110A and the bridge 130. In one embodiment, RSTCLK 220has a clock rate of 50 MHz. In this embodiment, CLKIN 215 has a clockrate 100 MHz. PLL 225 of processor 110A operates to generate a processorclock 230 with a clock rate of 500 MHz. The division element divides theprocessor clock 230 by 5 to generate PCLKOUT 235 at 100 MHz. PCLKIN 240also has a clock rate of 100 MHz. It is noted that bridge 130 mayoperate according to the 50 MHz RSTCLK 220, the 100 MHz clock CLKIN 215,or may implement a PLL, such as PLL 225 of processor 110A, to generate,for example, an internal clock at almost any frequency.

[0028] Turning now to FIG. 2B, a block diagram of an alternativeembodiment of the system clocking of FIG. 2A is shown. In thisembodiment, the system clock 210 provides a single clock signal overmore than one clock line. As shown, system clock 210B outputs a systemclock 215 that is routed as both CLKIN 215 and RSTCLK 220B. Thus, in oneembodiment both RSTCLK 220B and CLKIN 215 have a clock rate of 100 MHz.

[0029] It is noted that the ratio between CLKIN 215 and RSTCLK 220 ispreferably an integer greater than or equal to one. Thus, the ratiobetween CLKIN 215 and RSTCLK 220 may be 1, 2, 3, etc. It is also notedthat in a preferred embodiment, there is a minimal phase differencebetween a rising edge of CLKIN 215 and a corresponding rising edge ofRSTCLK 220.

[0030] Turning now to FIG. 3, a block diagram of an embodiment of one ofthe processors 110A and the bridge 130 of FIG. 1 is illustrated. Theexemplary details of the processor 111A, as shown in FIG. 3, includeinputs of a processor clock frequency ratio, shown as FID[3:0] 305, amodel specific register (MSR) 375, and a SIP receive logic 370. Also asillustrated, bridge 130 accepts inputs for the FID[3:0] 305, inputs forsystem configuration 304, a SIP ROM 365, and SIP send logic 360.

[0031] As shown, the SIP send logic 360 of the bridge 130 receives CLKIN215 and RSTCLK 220. The SIP send logic 360 is also coupled to receivethe FID[3:0] 305 values, the system configuration data 304, as well asdata read from the SIP ROM 365.

[0032] Also as shown, the SIP receive logic 370 accepts PCLK 230,PCLKOUT 235, and RSTCLK 220 as inputs, as well as the processor clockfrequency ratio FID[3:0] 305 and values read from MSR 375. The FID[3:0]305 values are input to the MSR 375 as well as provided to the SIPreceive logic 370. It is noted that the SIP ROM 365 may include aplurality of configuration sets. In one embodiment, the SIP ROM 365 isindexed by the length of the motherboard to which the bridge 130 isattached and by the frequency ID FID[3:0] values. Other methods ofindexing a particular configuration set for retrieval from the pluralityof configurations stored in the SIP ROM 365 are also contemplated.

[0033] The SIP send logic 360 outputs, as shown, RESET#310, CONNECT 320,and CFR (Clock Forward Reset) 325. Each of RESET#310, CONNECT 320, andCFR 325 are buffered into processor 110A and provided to the SIP receivelogic 370. The SIP receive logic 370 provides the PROCRDY 330 signal tothe bridge 130, where the PROCRDY signal 330 is provided to the SIP sendlogic 360.

[0034] Turning now to FIG. 4, an embodiment of one of the processors110A and the bridge 130 of FIG. 1 is shown. Also shown are exemplaryaddress, data, and control signals exchanged between the processor 110Aand the bridge 130. The CFR signal 325 is sent from the bridge 130 toprocessor 110A, where the CFR signal 325 is buffered into the processor110A. Address in lines SADDIN[14:2]# 410 are provided from the bridge130 to the processor 110A. A corresponding source-synchronous clock lineSADDINCLK# 405 is provided to clock the data on the SADDIN[14:2]#address lines 410. Likewise, the address out lines SADDOUT[14:2]# 420are provided from the processor 110A to the bridge 130. Correspondingaddress out clock line SADDOUTCLK# 415 is provided to clock the addresson the SADDOUT[14:2]# address lines 420. As illustrated, 64 data lines,which make up the SDATA[63:0]# 430 lines, bi-directionally transmit databetween the processor 110A and the bridge 130. A plurality of data inclock lines SDATAINCLK[3:0]# 425 provide clocking for data transferredfrom the bridge 130 to the processor 110A. In a similar fashion, dataout clock lines SDATAOUTCLK[3:0]# 435 provides clocking for datatransferred out over the SDATA lines 430 from the processor 110A to thebridge 130. Similarly to previous figures, all lines are buffered intothe destination device, either the processor 110A or the bridge 130, asshown in FIG. 4.

[0035] Turning now to FIG. 5, a block diagram of an embodiment of asystem for transferring a serial data stream from one device to anotherdevice is illustrated where the sending device operates according to adifferent internal clock than the receiving device. In a preferredembodiment, the ratio between the faster clock and the slower clock isan integer greater or equal to 1. As shown in FIG. 5, data stored in aSIP ROM 365 is transferred to and from SIP send logic 360. SIP sendlogic 360 is coupled to SIP receive logic 370 over connect line 320. Asshown, SIP receive logic 370 includes a first storage element 510, suchas a flop, which preferably clocked on a rising edge of RSTCLK 220. Dataoutput from storage element 510 is provided to storage element 520 andthe storage element 515. The storage element 515 latches the data inpreferably on a rising edge of RSTCLK 220. Storage element 520preferably latches in data on a falling edge of PCLKOUT 235.

[0036] Data output by storage element 515 is latched into storageelement 525 preferably on a falling edge of PCLKOUT 235. Data outputfrom storage element 525 is clocked into storage element 535 preferablyon a falling edge of PCLK 230. Data stored in storage element 520 isprovided to storage element 530. Storage element 530, preferably latchesin data from the falling edge of PCLK 230. Storage elements 530 and 535are each enabled by conditional enable signal 550 provided by controllogic 540. Upon latching data, storage elements 530 and 535 providetheir data to the control logic 540.

[0037] Control logic 540 is further coupled to a counter 555 that isconfigured to count clock edges for control logic 540. Data provided tothe control logic 540 may be stored in machine specific registers MSR375 as desired. As shown, control logic 540 is also configured to readdata from the MSR 375.

[0038] Generally speaking, a serial data stream stored in the SIP ROM365 is read by the SIP send logic 360 and provided to the SIP receivelogic 370 over connect line 320. A preferred embodiment of the SIPstream includes a start bit followed subsequently by a logic 370 latchesthe start bit into storage element 510 on a rising edge of RSTCLK 220.The SIP receive logic 370 then latches the start bit in storage element515 concurrently with latching in the ratio bit in storage element 510.Both storage elements 510 and 515 prefer the latch on the rising edgeRSTCLK 220. The start bit is latched into storage element 525 on thefalling edge of PCLKOUT 235 concurrently with the ratio bit beinglatched into storage element 520.

[0039] In a similar fashion, a start bit is latched into storage element535, the ratio bit is latched to the storage element 530. The controllogic 540 is configured to enable storage in storage elements 530 and535 during the appropriate edge of the processor clock (PCLK 230). Thecontrol logic 540 monitors the output of storage element 535 for thestart bit and concurrently decodes the ratio bit from storage element530 upon receiving the start bit from storage element 535. The ratio bitis stored in the MSR 375. The control logic is further configured to usethe ratio bit to configure counter 555 for timing of the next enablementof the conditional enable line 550. Additional details on the timing andflow of the method of transferring the SIP data stream between the SIPsend logic 360 and the SIP receive logic 370 over connect line 320 aregiven below with respect to FIGS. 6A and 6B.

[0040]FIG. 6A is an exemplary timing diagram of an embodiment of theoperations of the system shown in FIG. 5 when the sending device isclocked at a base clock rate that is equal to the clock rate of thereceiving device. Shown in FIG. 6A are RSTCLK 220, CLKIN 215, PCLKOUT235, PCLK 230, and the conditional enable signal 550. As shown, RSTCLK220, CLKIN 215 and PCLKOUT 235 operate according to equal clock rates.In other words, RSTCLK 220 and CLKIN 215 have a ratio of 1. PCLK 230 isillustrated with a clock rate 10 times the rate of CLKIN 215. This valueof 10 corresponds to the decode of the processor clock ratio FID[3:0],which was discussed above and will be further discussed below.

[0041] On a rising edge of RSTCLK 220, start bit is received at storageelement 510 (reference numeral 605A). On a next rising edge of RSTCLK220, a ratio bit is received at storage element 510 concurrently withthe start bit being received by storage element 515 (reference numeral610A). The start bit is received at storage element 525 and the ratiobit is received at storage element 520 on the next falling edge ofPCLKOUT 235 (reference numeral 615A).

[0042] A predetermined time later, as determined by the control logic540 shown in FIG. 5, the start bit is latched in the storage element 535and the ratio bit is latched into storage element 530 (reference numeral620A). On the next edge of PCLK 230, the ratio bit is read into controllogic 540 (reference numeral 625A). It is noted that the conditionalenable signal 550 is asserted for a predetermined period of timesubsequent to the start bit being latched into storage element 525 andthe ratio bit being latched into storage element 520, as shown inreference numeral 615A. As illustrated, the conditional enable signal550 is asserted for one clock period.

[0043] It is noted that the ratio bit being read into control logic 540and reference numeral 625A decodes with a value of 1. Thus, as in theillustrated embodiment, a known number of bit times will occur betweenvalid SIP bits as shown in reference numeral 650A. In the illustratedembodiment, that number of bit times is equal to the processor ratio 10multiplied by the ratio bit 1 multiplied by 2 bit times per clockperiod. Thus, there are approximately 20 bit times between valid SIPbits (reference numeral 650). It is noted that the bit times arepreferably measured with respect to PCLK 230, although other clock edgesmay be used as desired. In a preferred embodiment, the delay between thefalling edge of PCLKOUT 235 (reference numeral 615A) and the fallingedge of PCLK 230 (reference numeral 620A) is at least 4 PCLK phases (orbit times, as shown).

[0044] On a next rising edge of RSTCLK 220 the next SIP bit is receivedinto storage element 510 (reference numeral 630A). On the next fallingedge of PCLKOUT 235, the next SIP bit is received at storage element 520(reference numeral 635A). The known number of bit times between thevalid SIP bits later (reference numeral 650A), the condition enablesignal 550 is asserted and the next SIP bit is latched into storageelement 530 (reference numeral 640A). On the next edge of PCLK 230, thenext SIP bit is read into the control logic 540 (reference numeral645A).

[0045] On a next rising edge of RSTCLK 220 the next SIP bit is receivedinto storage element 510 (reference numeral 655A). On the next fallingedge of PCLKOUT 235, the next SIP bit is received at storage element 520(reference numeral 660A). The known number of bit times between thevalid SIP bits later (reference numeral 650A), the condition enablesignal 550 is asserted and the next SIP bit is latched into storageelement 530 (reference numeral 665A). On the next edge of PCLK 230, thenext SIP bit is read into the control logic 540 (reference numeral670A).

[0046] The SIP bits are read into the SIP receive logic 370 one bit at atime in a corresponding fashion until the end of the SIP data stream. Ina preferred embodiment, the total number of bits in the SIP data streamis predetermined. In other embodiments, a control signal orpredetermined data sequence may be used to terminate the SIP datastream.

[0047] Turning now to FIG. 6B, an exemplary timing diagram of anotherembodiment of the operations of a system of FIG. 5 are illustrated. Asshown, the sending device it clocked at a base clock rate that is onehalf the base clock rate of the receiving device. In FIG. 6B, CLKIN 215and PCLKOUT 235 are shown with the same clock rate as were previouslyseen in FIG. 6A. PCLK 230 is also shown with the same processor clockratio of 5 as seen in FIG. 6A. RSTCLK 220, however, is shown with aclock period that is twice that of CLKIN 215.

[0048] SIP data stream transfer between SIP send logic 360 and SIP sendlogic 370 occurs as follows in FIG. 6B. Start bit received at storageelement 510 on a rising edge of RSTCLK 220 (reference numeral 605B). Theratio bit is received at storage element 510 concurrently with the startbit latched into storage element 515 on the next rising edge of RSTCLK220 (reference numeral 610B). On the next falling edge of PCLKOUT 235,start bit is latched in the storage element 525 and the ratio bit islatched in the storage element 520 (reference numeral 615B).

[0049] A predetermined amount of time after the falling edge of PCLKOUT235, the start bit is latched into storage element 535 and a ratio bitis latched in storage element 530 (reference numeral 620B). Thecondition enable signal 550 is asserted appropriate for latching thestart bit and the ratio bit the appropriate time after the falling edgeof PCLKOUT 235, similar to what is shown in FIG. 6A. On the next edge ofPCLK 230, the ratio bit is read into the control logic 540 (referencenumeral 625B). As before, the control logic 540 preferably stores theratio bit in MSL 375 and uses the ratio bit to activate the counter suchthat the condition enable signal can be asserted at the appropriate bittime to read the next valid SIP bit. Now knowing the ratio bit value,the control logic 540 is configured to determine the known number of bittimes between valid SIP bits as shown (reference numeral 650).

[0050] The calculation, as before, involves the processor clock ratiovalue 10 multiplied by the ratio bit which is 2 in this example,multiplied by the 2 edges per clock. Thus, approximately 40 bit timesare illustrated between the edge of PCLK 230 upon which the SIP bits areread into the control logic 540 as shown at reference numeral 650B.

[0051] On the next rising edge of RSTCLK 220, the next SIP bit isreceived at storage element 510 (reference numeral 630B). On the nextfalling edge of PCLKOUT 235 the next SIP bit is latched into storageelement 520 (reference numeral 635B). After the predetermined delay, thenext SIP bit is clocked into storage element 530 when the conditionalenable 550 is asserted (reference numeral 640B). On the next edge ofPCLK 230, the next SIP bit is read into control logic 540 (referencenumeral 645B).

[0052] Likewise, additional SIP bits are received and latched intostorage element 510 (reference numeral 655B) on the rising edges ofRSTCLK 220. The additional SIP bits are further received at storageelement 520 (reference numeral 660B) on the subsequent falling edge ofPCLKOUT 235 (reference numeral 660B). Again, after the predeterminedperiod of time (see reference numeral 650B) has passed, the additionalSIP bits are received at storage element 530 (reference numeral 655B),on a falling edge of PCLK 230. The additional SIP bits are read into thecontrol logic 540 on the subsequent rising edge of PCLK 230 (referencenumeral 670B). The conditional enable 550 is asserted by the controllogic 540 the appropriate number of bit times since the previous validSIP bit (see reference numeral 650B).

[0053] Turning now to FIG. 7, a flowchart of an embodiment of a methodfor initiating operation of the computer system 100 of FIG. 1 isillustrated. The flowchart, as illustrated, is a high level flowchartand, as such, contains broad descriptions of one embodiment of a methodfor initiating the operations of the computer system 100. As shown, themethod comprises inputting a processor clock rate (step 710),initializing the processor 110A and the bridge 130 (step 720), andinitializing source-synchronous clocking between the processor 110A andthe bridge 130 (step 730). Details of a preferred embodiment for each ofthese steps 710, 720 and 730 are given below with respect to FIGS. 8, 9and 10.

[0054] Turning now to FIG. 8, a flowchart of an embodiment of a methodfor inputting the processor clock rate ratio to the processor, such asis shown in FIG. 7 at step 710 is illustrated. As shown, the methodcomprises the processor operating at the system clock frequency rate(step 810). The system clock may include RSTCLK 220 or CLKIN 215. It isnoted that the system clock frequency may comprise a frequency of, forexample, 50 MHz, 100 MHz, or other frequency as desired. It is notedthat in various embodiments, the system clock frequency may comprise arelatively slow clock, such that synchronous data transfers may beprovided between devices in the computer system 100 at the system clockfrequency.

[0055] The method also includes the processor tristating the frequencyID pins FID[3:0] 305 (step 820). The method further includes theprocessor sampling and decoding the processor clock frequency ratio fromthe frequency ID pins (step 830). The method also includes the bridge130 sampling the processor clock frequency ratio from the frequency ID305 signals as well as the bridge 130 sampling other systemconfiguration data from other pins or inputs (step 840). In a preferredembodiment, the processor clock frequency ratio is sampled fromdifferent signal lines by the processor and the bridge. The processorclock frequency ratio decoded is the same in this preferred embodiment.

[0056] It is noted that the frequency ID pins FID[3:0] 305 may bededicated pins or dual use pins, as desired. It is also noted that thefrequency ID pins 305 may provide the same signal to both the processor110A and the bridge 130 through the same pins or through differing pinsfor each device. Likewise, the additional system configuration datasampled by the bridge in step 840 may be through the use of dedicatedpins or signal line or multiple use pins or signal lines, as desired.

[0057] Turning now to FIG. 9, a flowchart of an embodiment or method forinitializing the processor 110A using a SIP stream is illustrated. Themethod illustrated in FIG. 9 may, for example, be step 720 of the methodof FIG. 7.

[0058] The method comprises system asserting the reset# signal 310, theconnect line 320, and/or the CFR signal 325 (step 905). The method alsocomprises a processor asserting the PROCRDY signal line 330 (step 910).The method next includes the system deasserting the reset# signal 310and/or the connect signal 320 (step 915). The processor deasserts thePROCRDY signal 330 (step 920). A time delay of one or more system clockperiods may optionally occur (step 925).

[0059] The system deasserts the CFR signal 325 (step 930). The processormonitors the connect signal 320 for the start bit (step 935). Anoptional time delay of one or more system clock periods may occur (step940).

[0060] The system transmits the serial SIP stream over the connectsignal line 320 (step 945). The system next asserts and holds theconnect signal line 320 (step 950). An optional time delay of one ormore system clock periods may occur (step 955). The processor assertsthe PROCRDY signal 330 (step 960), preferably to indicate that theprocessor 110A is ready for operation.

[0061] It is noted in step 910 that when the processor asserts thePROCRDY signal 330, that the processor may at this time, in oneembodiment, convert from running at the system clock frequency to theprocessor clock frequency. This changeover preferably occurs as a slowramp-up in the PLL 225. When the processor is operating at the processorfrequency, instead of the system clock frequency, the processor willdeassert the PROCRDY signal 330 in step 920.

[0062] Turning now to FIG. 10, a flowchart of an embodiment of a methodfor initializing source-synchronous clocking between one of theprocessors and the bridge of FIG. 1 is illustrated. While the processor110A is operating at the system clock frequency, either RSTCLK 220 orCLKIN 215, transfers between the processor 110A and the bridge 130 aresynchronous transfers at the RSTCLK 220 or CLKEND 215 frequency. Themethod of FIG. 10 converts transfers between the processor 110A and thebridge 130 from synchronous transfers to source-synchronous transfers,also known as clock forwarded transfers.

[0063] As shown, the method comprises that after a time delay of one ormore system clock periods after the processor asserts PROCRDY 330 instep 960, the system deasserts clock forward reset 325 signal (step1010). The processor samples the CFR signal 325 during the next systemclock (step 1020). Three system clock cycles after the system deassertsthe CFR 325 signal in step 1010, and two system clock cycles after theprocessor samples the CFR signal in step 1020, the processor drives itssource-synchronous clocks to the system (step 1030). The system drivesits source-synchronous clocks to the processor ( step 1040). It is notedthat in a preferred embodiment the processor drives itssource-synchronous clocks to the system concurrently with the systemdriving its source-synchronous clocks to the processor.

[0064] It is noted that in various embodiments, the start bit and theratio bit may be embodied as multiple bits. In other words, there may beone or more start bits and one or more ratio bits at the beginning ofthe SIP stream. The SIP receive logic only requires one start bit evenif there are multiple ratio bits. If there are multiple ratio bits,additional chains of storage elements are linked between storage element515 and 525 similar to the way in which storage elements 515, 525, and535 are linked between storage elements 510 and 520. Thus, when thestart bit reaches the last storage element in the chain, the ratio bitsmay be read from the storage elements at the end of the earlier storageelement chains by the control logic 540. It is noted that like storageelement 530 and 535, this last storage element should be clocked on thefalling edge of PCLK 230 and enabled by conditional enable signal 550from control logic 540. It is also noted that multiple start bits may beused to ensure that noise over connect 320 is minimized so that thestart of the SIP stream may be recognized. The encoding of the one ormore start bits and the encoding of the one or more ratio bits may bedesigned for the appropriate system.

[0065] Numerous variations and modifications will become apparent tothose skilled in the art once the above disclosure is fully appreciated.It is intended that the following claims be interpreted to embrace allsuch variations and modifications.

What is claimed is:
 1. A method for communicating a serial data streambetween a transmitter and a receiver, wherein the transmitter operatesaccording to at least a first clock having a first clock rate, whereinthe receiver operates according to at least a second clock having asecond clock rate, wherein a ratio between the second clock rate and thefirst clock rate is an integer number greater than or equal to one, themethod comprising: storing a start bit in a first storage element inresponse to the first clock; storing a ratio bit in a second storageelement in response to the first clock subsequent to said storing thestart bit in the first storage element; sampling the start bit inresponse to the second clock; sampling the ratio bit in response to thesecond clock; detecting the start bit following said sampling the startbit in response to the second clock; and sampling subsequent bitsfollowing the ratio bit at a rate dependent upon said ratio bit.
 2. Themethod of claim 1, further comprising: storing the start bit in a thirdstorage element following said sampling the start bit in response to thesecond clock; and storing the ratio bit in a fourth storage elementfollowing said sampling the ratio bit in response to the second clock.3. The method of claim 2, wherein said receiver is further configured tooperate according to a fast clock having a fast clock rate, wherein theratio of the fast clock rate to the second clock is a second integernumber greater than 1, the method further comprising: sampling the startbit in response to the fast clock; storing the start bit in a fifthstorage element following said sampling the start bit in response to thefast clock; sampling the ratio bit in response to the fast clock; andstoring the ratio bit in a sixth storage element following said samplingthe ratio bit in response to the fast clock.
 4. The method of claim 3,wherein said sampling the start bit in response to the fast clock andsaid sampling the ratio bit in response to the fast clock occurconcurrently on an edge of the fast clock.
 5. The method of claim 4,wherein said sampling the start bit in response to the fast clock andsaid sampling the ratio bit in response to the fast clock occur apredetermined period of time after said storing the start bit in thethird storage element and the predetermined period of time after saidstoring the ratio bit in the fourth storage element.
 6. The method ofclaim 1, wherein said first storage element and said second storage areone storage element, the method further comprising: storing the startbit in another storage element concurrently with said storing the ratiobit in the second storage element.
 7. A method for initiating a serialdata stream between a transmitter and a receiver, wherein thetransmitter operates according to at least a first clock having a firstclock rate, wherein the receiver operates according to at least a secondclock having a second clock rate, wherein a ratio between the secondclock rate and the first clock rate is an integer number greater than orequal to one, the method comprising: providing a first state over aserial line between the transmitter and the receiver; providing one ormore start bits over said serial line, wherein said one or more startbits indicate a second state different from said first state; providingone or more ratio bits over said serial line after said start bit,wherein said one or more ratio bits indicate said ratio between thesecond clock rate and the first clock rate; receiving said one or morestart bits; using a transition between said first state and said secondstate evident in said receiving each of said one or more start bits toreceive said one or more ratio bits; and receiving a remainder of saidserial data stream at appropriate intervals of said second clock rate.8. The method of claim 7, wherein said receiving said one or more startbits occurs on an edge of said second clock, and wherein said using atransition between said first state and said second state evident insaid receiving each of said one or more start bits to receive said oneor more ratio bits occurs on an edge of said second clock.
 9. The methodof claim 8, wherein said receiver is further configured to operateaccording to a slow clock having a slow clock rate, wherein the ratio ofthe second clock rate to the slow clock rate is a second integer numbergreater than 1, the method further comprising: receiving said one ormore start bits on an edge of said slow clock prior to said receivingsaid one or more start bits on said edge of said second clock; andreceiving said one or more ratio bits on an edge of said slow clockprior to said using a transition between said first state and saidsecond state evident in said receiving each of said one or more startbits to receive said one or more ratio bits on said edge of said secondclock.
 10. A method for initializing a serial data stream between atransmitter and a receiver, wherein the transmitter operates accordingto at least a first clock having a first clock rate, wherein thereceiver operates according to at least a second clock having a secondclock rate, wherein a ratio between the second clock rate and the firstclock rate is an integer number greater than or equal to one, the methodcomprising: storing a start bit in a first storage element in responseto the first clock; storing a ratio bit in a second storage element inresponse to the first clock subsequent to said storing the start bit inthe first storage element; sampling the start bit in response to thesecond clock; sampling the ratio bit in response to the second clock;detecting the start bit following said sampling the start bit inresponse to the second clock; and determining a rate for sampling aremainder of said serial data stream dependent upon said ratio bit. 11.The method of claim 10, further comprising: storing the start bit in athird storage element following said sampling the start bit in responseto the second clock; and storing the ratio bit in a fourth storageelement following said sampling the ratio bit in response to the secondclock.
 12. The method of claim 11, wherein said receiver is furtherconfigured to operate according to a fast clock having a fast clockrate, wherein the ratio of the fast clock rate to the second clock is asecond integer number greater than 1, the method further comprising:sampling the start bit in response to the fast clock; storing the startbit in a fifth storage element following said sampling the start bit inresponse to the fast clock; sampling the ratio bit in response to thefast clock; and storing the ratio bit in a sixth storage elementfollowing said sampling the ratio bit in response to the fast clock. 13.The method of claim 12, wherein said sampling the start bit in responseto the fast clock and said sampling the ratio bit in response to thefast clock occur concurrently on an edge of the fast clock.
 14. Themethod of claim 13, wherein said sampling the start bit in response tothe fast clock and said sampling the ratio bit in response to the fastclock occur a predetermined period of time after said storing the startbit in the third storage element and the predetermined period of timeafter said storing the ratio bit in the fourth storage element.
 15. Themethod of claim 10, wherein said first storage element and said secondstorage are one storage element, the method further comprising: storingthe start bit in another storage element concurrently with said storingthe ratio bit in the second storage element.
 16. A computer system,comprising: a memory configured to store initialization information forsaid computer system, wherein said initialization information beginswith a start bit and a ratio bit, wherein said ratio bit is encoded withsaid ratio between a second clock rate and a first clock rate; logiccoupled to said memory for transmitting said initialization information,wherein said logic is configure to operate according to said first clockrate, and wherein said logic is configured to transmit saidinitialization information at said first clock rate; at least oneprocessor coupled to receive a first system clock operating at saidfirst clock rate and a second system clock operating at said secondclock rate, wherein said at least one processor is configured to operateaccording to said second system clock, wherein a ratio between saidsecond clock rate and said first clock rate is an integer number greaterthan or equal to one, wherein said at least one processor is furthercoupled to said logic with a serial line over which to receive saidinitialization information; wherein said logic is configured transmitsaid initialization information over said serial line to said at leastone processor, wherein said logic is further configured to transmit afirst state over said serial line prior to said start bit, wherein saidstart bit includes a second state different from said first state,wherein said at least one processor is further configured to receivesaid start bit and to use a transition between said first state and saidsecond state evident in receiving said start bit to receive said ratiobit, and wherein said processor is further configured to decode saidratio bit to determine said first clock rate to receive a remainder ofsaid initialization information.
 17. The system of claim 16, whereinsaid at least one processor is further configured to operate at a fastclock rate, wherein the ratio between said fast clock rate and saidsecond clock rate is an integer greater than or equal to one.
 18. Thecomputer system of claim 16, further comprising: a bridge that includessaid memory and said logic.
 19. An apparatus for receiving a serial datastream clocked at a first clock rate, wherein said apparatus isconfigured to operate according to a fast clock rate that is a multipleof a second clock rate, wherein a ratio between the second clock rateand the first clock rate is an integer number greater than or equal toone, the apparatus comprising: a first register coupled to receive theserial data stream, wherein said first register is configured to latchbits upon an edge of a clock operating at said first clock rate; asecond register coupled to receive an output of said first register,wherein said second register is configured to latch bits upon an edgesaid clock operating at said first clock rate; a third register coupledto receive an output of said first register, wherein said third registeris configured to latch bits upon an edge of a clock operating at saidsecond clock rate; a fourth register coupled to receive an output ofsaid second register, wherein said fourth register is configured tolatch bits upon an edge of said clock operating at said second clockrate; a fifth register coupled to receive an output of said thirdregister, where said fifth register is enabled only for a predeterminedperiod after said edge of said clock that latches said third register,wherein said fifth register is configured to latch bits upon an edge ofsaid fast clock; a sixth register coupled to receive an output of saidfourth register, where said sixth register is enabled only for apredetermined period after said edge of said clock that latches saidfourth register, wherein said sixth register is configured to latch bitsupon an edge of said fast clock; logic coupled to receive an output ofsaid fifth register and said sixth register, wherein said serial datastream begins with a start bit indicating a state on a serial linedifferent from an initial state on said serial line, wherein said startbit is followed by a ratio bit indicating a ratio between said secondclock rate and said first clock rate, wherein said logic receives saidratio bit from said fifth register concurrently with receiving saidstart bit from said sixth register, wherein said logic adjusts saidpredetermined period based on a decode of said ratio bit.
 20. Theapparatus of claim 19, wherein said first register and said secondregister latch on a rising edge of said clock operating at said firstclock rate.
 21. The apparatus of claim 19, wherein said third registerand said fourth register latch on a falling edge of said clock operatingat said second clock rate.
 22. The apparatus of claim 19, wherein saidfifth register and said sixth register latch on either edge of said fastclock.